The present invention relates generally to integrated circuits, and more particularly, to a method of forming a high precision analog capacitor for use in an integrated circuit.
The manufacturing of semiconductor devices is a combination of the creation of a variety of components that collectively perform functions of data manipulation (logic functions) and of data retention (storage functions). The vast majority of these functions operate in a digital or on/off mode, and as such, recognizes xe2x80x9czeroxe2x80x9d and xe2x80x9conexe2x80x9d conditions within the operational levels of the circuits. There are, in addition, applications that make use of analog levels of voltage, for example, wherein the voltage may have a spectrum of values between a high limit and a low limit. Furthermore, applications exist where both digital and analog methods of signal processing reside in the same semiconductor device.
A mixture of functions and processing capabilities brings with it a mixture of components that can co-exist within one semiconductor device. Where the vast majority of device components is made up of transistors and a variety of switching components that address logic processing functions, it is not uncommon to also see resistors and capacitors that form part of a semiconductor device. For instance, it is known that capacitors form a basic component of many analog circuits that are used for analog applications such as analog-to-digital and digital-to-analog data conversion. Besides A/D conversion, capacitors perform a variety of critical tasks required to interface digital data with the external world, such as amplification, pre-filtering demodulation and signal conditioning. It is also well known in the art that capacitors are widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. In general, an analog capacitor stores information in various states, whereas a digital capacitor stores information in two states, namely, low and high. Typical analog applications involve analog-to-digital or digital-to-analog data conversion. Beside data conversion
In reference to the manufacture of analog capacitors, FIG. 1A illustrates a cross-sectional view 100 of a conventional analog capacitor 105, and FIG. 1B illustrates a conventional method 150 of fabrication of said capacitor. One of the first processing steps that is required in forming the capacitor 105 on the surface of a semiconductor substrate 110 is to electrically isolate the active regions (the regions where transistor devices will be created) on the surface of the substrate. Act 160 of FIG. 1B isolates the device 105 from other devices (not shown) on the semiconductor substrate 110 by forming a field oxide (FOX) 115. One conventional approach in the semiconductor industry for forming the FOX 115 is by the Local Oxidation of Silicon (LOCOS) method. LOCOS typically uses a patterned silicon nitride (Si3N4) layer (not shown) as an oxidation barrier mask, wherein the underlying silicon substrate 110 is selectively oxidized. One disadvantage of utilizing LOCOS is that a non-planar surface of the semiconductor substrate results. Another method of forming the field oxide (FOX) is to utilize Shallow Trench Isolation (STI) (not shown). One method of utilizing STI is to first etch trenches (not shown) having essentially vertical sidewalls in the silicon substrate. The trenches are typically then filled with a Chemical Vapor Deposition (CVD) of silicon oxide (SiO2) and the silicon oxide is then plasma etched or planarized using CMP to form an STI region which is significantly planar.
Following the formation of the FOX 115, a polysilicon layer 120 is formed over the FOX 115 in act 162 of FIG. 1B to define a bottom plate 121 of a capacitor 105. A silicide layer 125 is subsequently formed over the polysilicon layer 120 in act 164 to form a conductive etch stop over the polysilicon layer. The formation of the polysilicon layer 120 typically forms a vertical step 127 on the surface of the substrate 110. Unfortunately, this vertical step 127 results in deleterious effects when forming the capacitor 105 in the prior art, as will be described hereafter.
Subsequent to forming the polysilicon layer 120 and silicide layer 125, an oxide layer 130 is blanket deposited over the substrate in act 166 of FIG. 1B, typically by Low Pressure Chemical Vapor Deposition (LPCVD) to form a dielectric layer for the capacitor 105. A titanium nitride (TiN) layer 135 is then deposited over the substrate 110 in act 168 of FIG. 1B. A titanium nitride (TiN) hard mask layer 137 which is selective with respect to the underlying TiN layer 135 is furthermore formed over the TiN layer 135 in act 170. A capacitor masking pattern (not shown) is formed in act 172, whereby a subsequent hard mask etch and TiN etch are performed in act 174, thereby removing portions of the TiN hard mask layer 137 and TiN layer 135 to define a top plate 140 of the capacitor 105.
Following the TiN etch of act 174, an Interlayer Dielectric (ILD) layer 142 is formed by conventional methods. A contact masking pattern (not shown) is formed over the ILD layer 142 in act 178 of the prior art, and the ILD layer is etched in act 180 to form contact holes 143. A metal 144 is deposited over the ILD layer 142 in act 182, thereby filling the contact holes 143, and the metal is subsequently planarized in act 184. A wiring layer 145 in then formed over the contact holes 143 to interconnect the capacitor 105 to other devices (not shown) on the semiconductor substrate 110.
Due to the prior art method 150 utilizing a TiN layer 135 for a top plate 140 of the capacitor 105, the TiN etching performed in act 174 is critical, since the etch must stop at the semiconductor substrate 110 in order to avoid pitting of the semiconductor substrate. The etch must also be sufficient enough, however, to remove the TiN layer 135 residing over the silicide layer 125 in order to avoid stringers, (i.e., un-etched TiN residing on the suicide layer), which could potentially cause leakage in operation of the capacitor 105. Accordingly, the TiN etch process of act 174 must be monitored closely in order to avoid the deleterious effects of both over-etching into the semiconductor substrate 110 as well as under-etching the TiN layer 135. Furthermore, the step 127 of FIG. 1A caused by the formation of the polysilicon layer 120 over a non-planar surface of the substrate 110 accentuates the difficulty of the TiN etch when LOCOS is utilized in forming the FOX.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a method of forming an analog capacitor on a semiconductor substrate. More particularly, the invention relates to a method of forming a high precision analog capacitor over a field oxide (FOX) on a semiconductor substrate. According to the present invention, a field oxide layer is formed over a portion of the substrate. A polysilicon layer is formed over the field oxide layer, thereby defining a bottom plate of the capacitor, and a silicide is formed over the polysilicon layer, thereby defining a bottom plate of the capacitor. A first interlayer dielectric (ILD) layer is then formed over the substrate. According to one exemplary aspect of the invention, the first ILD layer comprises a plurality of layers.
Following the formation of the first ILD layer, a capacitor masking pattern is formed over the substrate, and an etching process is performed, wherein the first interlayer dielectric is etched using the capacitor masking pattern as a mask and the silicide as an etch stop, thereby defining a capacitor region. A thin dielectric is then formed over the substrate. According to another exemplary aspect of the present invention, the thin dielectric is formed by a low pressure chemical vapor deposition (LPCVD) process.
A contact masking pattern having one or more contact holes is formed over the substrate following the formation of the thin dielectric, and another etch process is performed, wherein the thin dielectric and the first interlayer dielectric are etched using the contact masking pattern as a mask and the silicide as an etch stop. According to yet another exemplary aspect of the invention, the contact masking pattern comprises a bottom plate capacitor contact hole and a moat contact hole, wherein the etching the thin dielectric and the first ILD layer comprises using the silicide as an etch stop for the bottom plate capacitor contact hole and the semiconductor substrate as an etch stop for the moat contact hole.
A metal layer is subsequently formed over the substrate, wherein the metal layer substantially fills the one or more contact holes. Furthermore, the metal layer is planarized, wherein a top plate of the capacitor and an electrical connection to the bottom plate of the capacitor are defined, and wherein the top plate of the capacitor and the electrical connection to the bottom plate of the capacitor are laterally isolated by the first ILD.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.